Huawei Mass-Produces Kirin 9050 Pro Logic-Folding Chip; ScaleFlux Targets AI Memory Bottleneck

At Huawei's terminal innovation technology communication meeting, Huawei Terminal BG CTO Li Xiaolong and Huawei semiconductor wireless terminal chip product management department head Xu Songyu described the Kirin 9050 series and the next steps for the company's chip roadmap. Huawei spent 192.3 billion yuan on research and development in 2025, or 21.8% of revenue, and its cumulative R&D spending from 2016 to 2025 reached 1.382 trillion yuan, the company said.

The Kirin 9050 Pro is the first mass-produced logic-folding chip under what Huawei calls Tao's law. Huawei said its team designed multiple dies as one chip from a three-dimensional perspective, laying them out in layers according to logic and connecting them with dense vertical interconnects. Data that previously had to travel around a flat plane can take a shorter path. The company said the Kirin 9050 series has more than 50 million hybrid bonds and more than 5 million effective signal interconnects. Its top metal pitch is 720 nanometers, and this generation's hybrid bonding pitch is 1.5 microns. According to Huawei's research, a ratio of less than 3 between the hybrid bonding pitch and the top metal pitch is an important condition for effective logic folding. Huawei reported a 53.5% increase in transistor density, but the communication meeting did not give an equivalent process-node conclusion for the density change.

Huawei said logic folding shortens critical paths, improves clock skew, reduces clock tree depth and cuts clock distribution overhead. Those changes can allow lower operating voltage and power savings. Compared with the Mate 80 Pro Max with the Kirin 9030 Pro, the Mate 90 Pro Max with the Kirin 9050 Pro has a 12.7% higher CPU frequency, 25% higher CPU performance, 40% higher GPU performance, 45% lower GPU power consumption, 140% higher NPU computing power and 66% lower NPU power consumption, according to Huawei's figures. Xu said a typical critical path between CPU cores and L1 and L2 cache can be split across two layers and connected by hybrid bonding, creating room for higher frequency.

The Kirin 9050 Pro's new Da Vinci architecture NPU is central to Huawei's local AI push. Huawei said running a 30-billion-parameter MoE model on a phone is difficult because memory is limited and high power consumption cannot be sustained. If all 30 billion parameters were stored at 4 bits, the weights alone would require about 15GB. The Kirin 9050 series uses multi-level storage-compute collaboration, loading hot experts into DDR while keeping experts not needed for the current computation in Flash, combined with low-bit quantization. With system-level optimization, Huawei said the chip can run a 30B MoE model with less than 2.5GB of additional memory. A scenario-adaptive scheme adjusts the number of parameters used according to task complexity. Huawei said this supports local AI experiences such as gallery organization, in which the phone can understand a user's intent, break down steps and create albums without a network connection.

Huawei also described changes in the image processing chain. The Kirin 9050 series' AI ISP adds a pixel-specific NPU inside the ISP and works with an external general-purpose NPU. The dual-engine architecture processes tasks in parallel to reduce queuing and interaction overhead. Huawei said the related processing latency can be kept within 16.7 milliseconds, matching the time budget for each frame of 4K 60-frame-per-second video. For display, Li said the second-generation Linglong display uses dual-layer OLED, but its display driver IC has limited storage for calibration data. Huawei lets the Kirin SoC participate in compensation: at high brightness the DDIC uses its power advantage, while at low brightness and other scenes requiring fine calibration, the SoC and display chip process the data together.

Xu said the next-generation “Kirin 2027” chip is already in Huawei's hands and all test results so far meet expectations. The evolution of Huawei's logic-folding chips includes shrinking hybrid bonding pitch, adding interconnects, bringing more modules into folding, exploring more layers and improving design tools, according to the report. Xu said each generation's need for more layers, larger cache or higher frequency will still be decided by product requirements. Chip and phone teams jointly define targets from user experience back to system metrics, then set chip specifications, architecture and technology. He also said heat and yield remain engineering issues. Shorter communication distances and critical paths can reduce communication power and improve overall energy efficiency, but temperature under different loads, local hot spots and sustained performance still require thermal design and testing. Yield will be improved with industry partners. “No single company can answer all the answers,” Xu said.

ScaleFlux is taking aim at a different part of the AI data pipeline. Hao Zhong, co-founder and CEO, said GPU and TPU performance has advanced almost more than 1,000 times in the last eight years, and the data pipeline must keep up or expensive compute will not deliver enough efficiency. He described AI infrastructure as a pipeline with processors and high-bandwidth memory in the first stage, external DRAM in the second and SSDs in the third. This year ScaleFlux unveiled controllers for PCIe Gen 6 SSDs and for Compute Express Link memory. Zhong said workloads are shifting from training toward inference and agentic work, which requires much more data close at hand. That makes capacity, bandwidth and performance in external DRAM and SSDs central to infrastructure decisions. “That's why the data storage and memory now becomes extremely important and literally become the bottleneck of the future AI,” Zhong said, according to SiliconANGLE.