MemSilicon Tapes Out 1Gb 1T4R RRAM Chip on 28nm CMOS

The device uses a 28nm CMOS platform and a 1T4R cell structure, with 1Gb of capacity per die, a density of 30Mb/mm² and an access latency below 20ns. It also integrates on-chip hardware error-correction circuitry, which the company says allows large capacity, high density and fast reading to be addressed together. The array is built with back-end-of-line integration that is fully compatible with the CMOS platform.

The approach is intended to answer a widening demand from high-performance SoCs, embodied-intelligence systems and AI PCs, which need to hold more weights, KV cache entries, parameters and data while keeping access latency, power consumption and cost under control. Existing options carry trade-offs: SRAM reads quickly but has a large cell area and low density, while embedded Flash faces growing integration difficulty as logic processes scale. RRAM, which is non-volatile and has high-density integration potential, has therefore become a leading candidate among emerging memory technologies.

According to public reports cited by QbitAI, Samsung, TSMC and GlobalFoundries have added RRAM to their advanced-node technology roadmaps, with TSMC listing RRAM support at 12nm and 6nm. On the customer side, Infineon has selected RRAM for microcontrollers at the 28nm node.

In a conventional 1T1R structure, one selector transistor serves one resistive cell, handling selection and access control while the resistive element stores the bit. As cell dimensions shrink, the transistor and its connections account for a growing share of area. The 1TnR route shares one transistor among several resistive cells, cutting the average transistor area per cell. MemSilicon says it is the originator of a 1TnR route compatible with standard CMOS processes, with technology traceable to the team of Liu Ming, an academician at the Chinese Academy of Sciences; that team published 28nm 1T2R RRAM research in 2020.

Sharing transistors does not scale density and performance proportionally. Non-target current paths between cells, read and write disturbance, and reliability across operating conditions all require joint optimization of device, process and circuit design. MemSilicon said MountTai 2026 introduces and validates several in-house techniques at the circuit and architecture level: a negative-voltage design and a unified reset circuit to suppress array leakage current, cut power and improve reliability; a multi-voltage-domain wordline driver that decouples high- and low-voltage read and write paths, together with an adaptive protection bias technique to lower mis-write risk; and an on-chip adaptive follower read circuit aimed at the read reliability and read yield problems that arise at gigabit-scale 1TnR capacity, paired with hardware error correction to form a dual read-assurance mechanism.

In September, the Ministry of Industry and Information Technology and the National Development and Reform Commission jointly issued the 15th Five-Year Plan for the development of the electronic information manufacturing industry, which lists resistive memory and other emerging memory products, as well as computing paradigms such as compute-in-memory, as development directions. MemSilicon, whose core team comes from the Chinese Academy of Sciences and Fudan University, said it is pursuing three product lines in response: embedded RRAM IP for display drivers, microcontrollers, SSD controllers and security chips, which it says is already entering customer scenarios; high-density, large-capacity RRAM, including further exploration of 1TnR structures, three-dimensional integration and storage needs tied to AI inference; and hybrid compute-in-memory that combines RRAM with DRAM for embodied intelligence, AI PCs and other edge inference uses, using hybrid 3D integration to shorten data movement paths.