Meta and Panmnesia Target Nearly 1,000 AI GPUs in One Coherent Data Center Domain

The effort targets a problem that grows as AI training systems combine hundreds or thousands of accelerators processing large amounts of data. Each accelerator must move through repeated computational stages, so one delayed component can force other devices to wait. The researchers focus on reducing unpredictable communication delays between racks, where Ethernet or InfiniBand networks usually handle connections beyond individual systems. Those networks require packet processing and software coordination, which can introduce greater latency variation as workloads spread across more servers. CXL instead provides a shared coherence mechanism, allowing processors, accelerators and memory to participate in one connected resource environment.

Panmnesia's proposed architecture adds dedicated hardware intended to keep communication paths and processing behavior more consistent across the larger fabric. The design uses a high-fan-out switch, a link acceleration unit and a fabric controller to manage traffic. These components are organized into trays, pods and a fabric, borrowing organizational principles normally associated with arranging functional blocks inside semiconductor chips. The company says its fabric controller and link acceleration unit have completed silicon validation, while its switch has already been fabricated. Pre-release silicon is reportedly being supplied as development continues toward commercial products.

The review compares the proposed arrangement with NVIDIA's GB200 NVL72, in which one CPU directly coordinates two accelerators through NVLink-C2C. Under Panmnesia's architecture, one CPU could coordinate 16 accelerators, an eightfold increase over that reference configuration. According to the published design, around 60 such groups could then form a coherence domain containing approximately 960 accelerators. Cross-rack access could also fall from microsecond-level timing to several hundred nanoseconds, roughly an order-of-magnitude reduction.

The architecture would allow individual failed devices to be replaced without taking an entire server out of service. That separation could reduce the amount of functioning hardware removed during failures, although the actual operational benefits would depend on implementation. During the announcement, Myoungsoo Jung, CEO of Panmnesia, said, “CXL enables the entire datacenter to operate as a single computing system.”

The design still faces physical limits because electrical CXL signaling reaches only about seven meters at 128 GT/s with two retimers. Panmnesia therefore proposes optical CXL links for longer distances and says it has already completed hardware proof-of-concept validation for that approach.