OpenAI's Nine-Month Chip Tape-Out Hides a Longer Road, Engineers Say

OpenAI's chip ambitions date back at least to 2023, when chief executive Sam Altman considered pushing for the construction of more than 30 fabs, according to Leiphone. The cost and long timelines deterred a company that is not even fabless; by 2024 OpenAI had shifted its focus to the part where it has an advantage, defining what its own models and inference services need from silicon.

According to OpenAI, AI has taken part in exploring implementation options for Jalapeño, in the design-measure-verify loop, in optimizing some arithmetic circuits, and in post-silicon debugging and programming. Mu Yang, a front-end design and verification engineer, estimated that this is roughly half a year faster than a design without AI assistance. Several industry practitioners told Leiphone that Broadcom's mature engineering capability is another essential piece. Its silicon implementation, networking and interconnect capability, interface IP and accumulated engineering system saved OpenAI the time of building底层 capabilities from scratch — and those proprietary knowledge systems do not automatically become OpenAI's own as general models improve.

Lu Jinian, product director at a chip company, said AI's role should not be understated. For a first-generation chip, he said, the more important outcome is proving a working flow in which AI participates in chip design; once that flow can be reused, the next generation does not have to explore the same path again, and human intervention can be reduced further. Given the complexity of Jalapeño's structure, Lu called nine months "quite good" but said OpenAI is capable of a six-month design cycle.

OpenAI has disclosed most clearly that AI has entered RTL, the register-transfer level stage where an architecture is turned into code describing digital circuits. Mu Yang, who had never worked in the field, said she used AI to generate and modify RTL in a RISC-V CPU development project after giving it performance targets, design constraints and test requirements. In the same project, a unit-test verification task that would previously have taken two experienced engineers about four months was completed by one person in roughly three weeks, from breaking down test points to confirming final results — a saving of more than 100 days, or an 80% efficiency gain.

The change has reached established chip companies. Nvidia disclosed this year that it used Cadence's AI agent for RTL verification, cutting work that once took five weeks to less than a day. A Cadence staff member said Altera, Qualcomm and Tenstorrent have also begun deploying similar agents, with Altera saying some verification workloads have been compressed to about one-tenth of their previous size. Lu Jinian said the latest model, GPT-6 Astra, can read waveforms, and its improved understanding of graphics and spatial relationships extends AI from writing circuits toward how circuits are placed and connected on a chip.

Even so, a gap remains between the full chip development cycle and the pace of model iteration. Jalapeño was publicly reported in late October 2024, and OpenAI plans initial deployment before the end of 2026, a span of about 26 months. Jim, a large-model practitioner who spoke under a pseudonym, said self-developed ASICs become commercially attractive only when AI agents compress the whole development chain to about 18 months, still short of model updates that arrive monthly.

Model changes do not always require new hardware. Jim said a new set of weights, adjustments to part of the computation, or changes in matrix size and arrangement can usually be handled through kernels, compilers and scheduling. The harder problem is when the ratio of compute, memory and communication matched for one generation no longer fits the next. In a mixture-of-experts model, the basic computation may not change, but data must move between experts and chips, and communication and storage pressure can jump. Changes to attention operators, or to whether tokens are generated serially or in parallel, can also shift the balance among storage, bandwidth and compute.

Jim said companies must weigh how much area, power and development cost they will pay for flexibility; how many models and scenarios a capability will cover; and whether the performance and cost gains of specialization justify the risk of betting on the wrong direction. Jalapeño itself reflects that uncertainty: OpenAI said the project early on considered a more decode-oriented design but ultimately chose one chip supporting both prefill and decode, leaving room for software adjustment.

Li Linyang, founder of AI chip design company Novasilicon, said AI still performs best on tasks with clear boundaries, such as RTL code implementation. The closer work moves to top-level architecture and specification definition, the harder it is for agents to intervene, because even human architects struggle to define clear boundaries in a vast search space. Final acceptance is similar. Mu Yang said engineers with 10 to 15 years of experience are still needed to make judgments, and that a stage where "a novice can design chips" will come only when AI's own verification and judgment能力 mature.