Cadence Executives Say AI Could Halve Chip Design Time, but Full Automation Still Years Away

Chung Ching-chin, senior vice president and general manager of the Digital & Signoff Group at Cadence, said AI-assisted design could reduce the time to design a chip on the same process node by roughly half. He estimated that a 30% reduction in tool runtime and a 30% reduction in engineering effort could combine to cut overall time to about 49%, effectively doubling design efficiency. The estimate excludes wafer fab scheduling, board development and mass production.

Chung's remarks followed OpenAI's release of first test results for its in-house inference chip, Jalapeño, which OpenAI said took only nine months from initial design to tapeout. AI was used to explore implementation options, shorten design, measurement and verification loops, and optimize some arithmetic circuits. OpenAI developed the chip with Broadcom, so it was not a case of AI independently designing a chip.

According to Lei Feng, a technology news outlet that reported Chung's comments, AI EDA is moving from point-tool optimization to end-to-end coordination. Cadence has introduced an Agentic AI Stack that integrates multiple tool stacks covering front-end design, analog design, digital implementation and signoff, PCB and advanced packaging, and system design. In a real project cited by Wang Xiaoyu, vice president and general manager of Cadence China, a large subsystem that traditionally took about five weeks to design and verify was completed in about one day using the ChipStack. In another case, AI achieved results comparable to a senior engineer on a 4nm high-performance CPU core design while reducing manual log analysis and constraint tuning.

Chung said AI could automate 70% to 90% of design blocks that are structurally simple and do not require extreme performance. But critical blocks such as CPUs, GPUs, NPUs and severely congested areas will still require senior engineers. Wang said that running a RISC-V design from source to GDSII only proves the flow works; the real question is whether a competitive CPU can be produced. The most difficult 10% of a design largely determines the chip's performance ceiling.

Three hurdles remain before full automation, Chung said. First, multiple AI agents must coordinate reliably. Many companies have developed small agents for specific tasks, but organizing them into a coherent workflow remains difficult. Cadence argues its top-down approach, driven by CEO Anirudh Devgan, gives it an advantage over fragmented agent development. However, conflicting judgments from different agents are still an unresolved technical issue.

Second, deterministic verification is essential. A model thinking a result looks reasonable is not sufficient; chips must meet strict timing, power and area constraints. At 3nm, 2nm and 1.4nm nodes, a single model hallucination could ruin a design. AI agents will not bypass traditional signoff tools such as Tempus and Pegasus. Cadence's "three-layer cake" model places AI on top, core algorithms in the middle, and accelerated computing at the bottom; AI can amplify but not fix flawed underlying algorithms.

Third, the economics must work. Chung disclosed that his team's monthly token spending has already reached a considerable level. AI EDA competition will involve not only which agent is smarter but also how many tokens are needed to complete a task and whether the return on investment is sufficient.

Chung said AI will first automate repetitive work, while engineers' value shifts to judgment. Engineers will spend less time memorizing commands, writing scripts and running flows, and more time defining problems, making architecture and PPA trade-offs, judging whether AI results are trustworthy, and handling the hardest blocks.

Wang emphasized that semiconductor fundamentals remain essential. Engineers who do not understand chip design cannot evaluate or challenge AI outputs. AI lowers the barrier to using EDA tools but raises the value of defining problems and validating results. Challenging an agent, rather than merely using it, becomes a path from junior to senior engineer.

The product form and business model of EDA may also change. As AgentStack becomes a unified entry point, engineers may simply describe a PPA target and let agents call underlying tools. Tool use disappears behind agents. Chung said Cadence's CEO and management are discussing how to commercialize agent capabilities, with a token-based model and value-based pricing among options. Wang said product lines still disagree on a unified pricing model. The ultimate standard will be measurable ROI for customers.

The industry is likely to move from selling tool licenses to charging by usage, productivity value or task results. Token cost becomes a new variable, creating both a new revenue channel and a new cost structure. The ability to complete complex design tasks with fewer tokens may become a key competitive factor in the next stage of AI EDA.

OpenAI's Jalapeño shows AI is already in real chip design and optimization flows. Cadence's assessment highlights the gap between AI-assisted design and AI independently producing a competitive chip. In the next five years, the more likely outcome is near-doubled design efficiency and a shift of engineers' focus from operating tools to defining goals and judging results, rather than fully unmanned chip design.